This invention relates to driver circuits responsive to applied input signals for sourcing current at a high impedance output. More particularly, the present invention relates to a monolithic driver circuit responsive to an applied input logic pulse signal for supplying an output logic signal having controlled and fixed slew rates, i.e., rise and fall times associated therewith; the driver circuit buffering the logic input signal drive circuitry from load circuitry coupled to the output of the driver circuit and capable of providing logic level shifting.
There are a myriad of applications wherein it is desirable to buffer input signal drive ciruitry from a load circuit while accurately reproducing the input signal drive across the load circuit. For example, one such application may require reproducing logic drive signals onto a serial data bus without distorting the data contained in the logic drive signal while eliminating high frequency noise components associated with the rise and fall times of the leading and trailing edges of the logic drive input signal.
For instance, most, if not all, automobile manufacturers use multi-wiring harnesses throughout the vehicle to control multi-functions including dashboard electronics, window control, and headlight control as well as other control functions. To simplify the wiring harness and to reduce manufacturing cost, at least one automobile manufacturer has proposed the use of only two wires serially driven by logic drive signals to control the aforementioned multi-functions. For instance, a microprocessor could be utilized to serially interface the serial data bus represented by the two-wire harness. In this system the microprocessor may be a CMOS drive circuit for driving CMOS logic control signals onto the serial data bus. The data information from the CMOS driver circuit in this application is contained in the pulsewidth of the CMOS logic signals, i.e., a logic one would have a pulsewidth more than twice the width of a pulse representing a logic zero.
It is recognized that the fast rise and fall times associated with the CMOS logic signals contain high frequency signal components that are undesirable in the automotive environment as these components can create amplitude modulated (AM) noise. Thus, it is necessary that the high frequency components of the logic signals be eliminated without distorting the data represented by the width of the data pulse, i.e., neither lengthening nor shortening the pulsewidth of these data pulses.
Hence, a driver-buffer circuit is required that is coupled between the logic drive circuitry and the serial data bus to buffer the logic input of the CMOS circuit from the serial data bus. Such a circuit must provide symmetrical rise and fall times to maintain the integrity of the applied logic signals while reducing the slew rates of the corresponding logic signals applied to the data bus.